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| 19-4653; Rev 1; 3/10 KIT ATION EVALU BLE AVAILA Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors General Description The MAX9670/MAX9671 dual SCART matrices route audio and video signals between a set-top box decoder chip and two external SCART connectors under I2C control. Operating from a 3.3V supply and a 12V supply, the MAX9670/MAX9671 consume 66mW during quiescent operation and 300mW during average operation when driving typical signals into typical loads. Video input detection, video load detection, and a 2.8mW standby mode facilitate the design of intelligent, low-power set-top boxes. The MAX9670/MAX9671 audio section contains a buffered crosspoint to route audio inputs to audio outputs and programmable volume control from -62dB to 0dB in 2dB steps. The DirectDrive(R) output amplifiers create a 2VRMS full-scale audio signal biased around ground, eliminating the need for bulky output capacitors and reducing click-and-pop noise. The zero-cross detection circuitry also further reduces clicks and pops by enabling audio sources to switch only during a zerocrossing. The MAX9671 offers TV left and right audio inputs. The MAX9670/MAX9671 video section contains a buffered crosspoint to route video inputs to video outputs. The standard-definition video signals from the settop box decoder chip are lowpass filtered to remove out-of-band artifacts. The MAX9670/MAX9671 also support slow-switching and fast-switching signals. An interrupt signal from the MAX9670/MAX9671 informs the microcontroller when the system status has changed. o 2.8mW Standby Mode Consumption o Programmable Audio Gain Control of -62dB to 0dB (TV Audio Outputs) o Clickless, Popless, DirectDrive Audio o Video Input and Video Load Detection o Video Reconstruction Filter with 10MHz Passband and 52dB Attenuation at 27MHz o 3.3V and 12V Supply Voltages Features o 66mW Quiescent Power Consumption MAX9670/MAX9671 Ordering Information PART MAX9670CTL+ TEMP RANGE 0C to +70C PINPACKAGE 40 TQFN-EP* TV R+L AUDIO INPUTS No Yes MAX9671CTH+ 0C to +70C 44 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. System Block Diagram V12 12V VVID 3.3V VAUD 3.3V Applications Set-Top Boxes TVs DVD Players STB CHIP I2C C INTERRUPT OUTPUT MAX9670/MAX9671 RGB, Y/C, CVBS I2C INTERFACE REGISTERS AND ACTIVITY MONITOR CVBS L/R AUDIO (MAX9671 ONLY) L/R AUDIO (MAX9670 ONLY) SLOW SWITCHING TV SCART VIDEO ENCODER RGB, Y/C, CVBS VIDEO FILTERS AND CROSSPOINT FAST SWITCHING STEREO AUDIO DAC SINGLE-ENDED R/L STEREO AUDIO AUDIO CROSSPOINT WITH DIRECTDRIVE OUTPUTS, VOLUME CONTROL Y/C, CVBS RGB, Y/C, CVBS L/R AUDIO SLOW SWITCHING VCR SCART SLOW SWITCHING FAST SWITCHING FAST SWITCHING Typical Application Circuit appears at end of data sheet. CHARGE PUMP DirectDrive is a registered trademark of Maxim Integrated Products, Inc. EP GNDVID ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 ABSOLUTE MAXIMUM RATINGS VVID to GNDVID........................................................-0.3V to +4V Audio Outputs to VAUD, EP .....................................Continuous V12 to EP.................................................................-0.3V to +14V TV_SS, VCR_SS to V12, EP......................................Continuous VAUD to EP ...............................................................-0.3V to +4V Continuous Power Dissipation (TA = +70C) EP to GNDVID .......................................................-0.1V to +0.1V 40-Pin TQFN-EP (derate 26.3mW/C above +70C) ...2105.3mW All Video Inputs, VCRIN_FS to GNDVID...................-0.3V to +4V 44-Pin TQFN-EP (derate 26.3mW/C above +70C)...2222.2mW All Audio Inputs to EP .........................................-1V to (EP + 1V) Junction-to-Case Thermal Resistance (JC) (Note 1) 40/44-pin TQFN-EP .........................................................1C/W SDA, SCL, DEV_ADDR, INT to GNDVID ..................-0.3V to +4V Junction-to-Ambient Thermal Resistance (JC) (Note 1) TV_SS, VCR_SS to EP .................................-0.3V to (V12 + 0.3V) Current 40/44-pin TQFN-EP .......................................................27C/W All Video/Audio Inputs ...................................................20mA Operating Temperature Range...............................0C to +70C C1P, C1N, CPVSS .........................................................50mA Junction Temperature ......................................................+150C Output Short-Circuit Current Duration Storage Temperature Range .............................-65C to +150C Video and Fast-Switching Outputs to VVID, Lead Temperature (soldering, 10s) .................................+300C GNDVID.................................................................Continuous Soldering Temperature (reflow) .......................................+260C Note 1: Package thermal resistance were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER Video Supply Voltage Range Audio Supply Voltage Range V12 Supply Voltage Range SYMBOL VVID VAUD V12 CONDITIONS Inferred from video PSRR test at 3V and 3.6V Inferred from audio PSRR test at 3V and 3.6V Inferred from slow-switching levels Normal operation; all video output amplifiers are enabled and muted (Note 3) VVID Quiescent Supply Current IVID_Q Standby mode, slow switch inputs low Shutdown VAUD Quiescent Supply Current IAUD_Q Normal operation (Note 3) Shutdown Normal operation (Note 3) Slow-switching output set to low-level Slow-switching output set to medium-level 0.3 475 10 A 3.2 MIN 3 3 11.4 TYP 3.3 3.3 12 16 MAX 3.6 3.6 12.6 30 1500 35 6 35 100 A UNITS V V V mA A mA A V12 Quiescent Supply Current I12_Q Shutdown, TA = +25C VIDEO CHARACTERISTICS DC-COUPLED INPUT RL = 75 to GNDVID or 150 to VVID/2; inferred from gain test VVID = 3V VVID = 3.135V VVID = 3.3V 1.3 1 300 1.15 Input Voltage Range VIN 1.15 VP-P Input Current Input Resistance IIN RIN VIN = 0.3V, TA = +25C 2 A k 2 _______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors ELECTRICAL CHARACTERISTICS (continued) (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER AC-COUPLED INPUT Sync-Tip Clamp Level Sync Crush Input Clamping Current Maximum Input Source Resistance Input Voltage VCLP Sync-tip clamp Sync-tip clamp; percentage reduction in sync pulse (0.3VP-P); guaranteed by input clamping current measurement, TA = +25C Sync-tip clamp, VIN = 0.3V, TA = +25C Input sync-tip circuit must be stable even if the source resistance is as high as 300 Bias circuit High-impedance input circuit Bias circuit High-impedance input circuit Av Guaranteed by output voltage swing Guaranteed by output voltage swing of TV_R/C_OUT, TV_G_OUT, and TV_B_OUT; first input signal set is VCR_R/C_IN, VCR_G_IN, and VCR_B_IN; second signal set is ENC_R/C_IN, ENC_G_IN, and ENC_B_IN Sync-tip clamp (VIN = VCLP) Bias circuit Sync-tip clamp, measured at output, VVID = 3V, VIN = VCLP to (VCLP +1.15V), RL = 150 to VVID/2, RL = 75 to GNDVID Measured at output, VVID = 3.135V, VIN = VCLP to (VCLP + 1.15V), RL = 150 to VVID/2, RL = 75 to GNDVID Output Voltage Swing Bias circuit, measured at output, VVID = 3V, VIN = (VBIAS - 0.575V) to (VBIAS + 0.575V), RL = 150 to VVID/2, RL = 75 to GNDVID Measured at output, VVID = 3.135V, VIN = (VBIAS - 0.575V) to (VBIAS + 0.575V), RL = 150 to VVID/2, RL = 75 to GNDVID Output Short-Circuit Current Output Resistance Output Leakage Current Power-Supply Rejection Ratio ROUT Output disabled (load detection not active) 3V VVID 3.6V 35 2.3 1.95 0.57 0.3 x VVID 10 222 2 2.05 1 300 0.6 0.63 0.36 x VVID V -13 -4 +6 2 2 mV % A SYMBOL CONDITIONS MIN TYP MAX UNITS MAX9670/MAX9671 Input Resistance DC CHARACTERISTICS DC Voltage Gain k V/V DC Gain Mismatch Among R, G, and B Outputs -2 +2 % Output Level 0.1 1.3 0.30 1.5 2.3 0.51 1.78 V 2.243 2.3 2.358 VP-P 2.243 2.3 100 0.5 2.358 mA 170 A dB _______________________________________________________________________________________ 3 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 ELECTRICAL CHARACTERISTICS (continued) (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER AC CHARACTERISTICS Filter Passband Flatness Filter Attenuation Slew Rate Settling Time Differential Gain Differential Phase 2T Pulse-to-Bar K Rating 2T Pulse Response 2T Bar Response Nonlinearity Group Delay Distortion Glitch Impulse Caused by Charge-Pump Switching Peak Signal to RMS Noise Power-Supply Rejection Ratio Output Impedance Video Crosstalk Reverse Isolation DG DP VOUT = 2VP-P, f = 100kHz to 5.5MHz VOUT = 2VP-P, attenuation is referred to 100kHz f = 9.5MHz f = 27MHz f = 54MHz -1 3 40 55 60 400 0.15 0.5 0.3 0.2 0.2 0.1 11 100 70 47 2 -80 92 V/s ns % Degrees K% K% K% % ns pV-s dB dB dB dB dB dB SYMBOL CONDITIONS MIN TYP MAX UNITS VOUT = 2VP-P, no filter in video path VOUT = 2VP-P, settle to 0.1% (Note 4) 5-step modulated staircase, f = 4.43MHz 5-step modulated staircase, f = 4.43MHz 2T = 200ns, bar time is 18s, the beginning 2.5% and the ending 2.5% of the bar time is ignored 2T = 200ns 2T = 200ns, bar time is 18s, the beginning 2.5% and the ending 2.5% of the bar time is ignored 5-step staircase 100kHz f 5MHz, outputs are 2VP-P Measured at outputs 100kHz f 5MHz f = 100kHz, 100mVP-P f = 5MHz f = 4.43MHz VCR SCART inputs to encoder inputs, full-power mode with VCR being looped through to TV, f = 4.43MHz Enable VCR_R/C_OUT pulldown through I2C interface VIN = -0.707V to +0.707V VIN = -0.707V to +0.707V f = 20Hz to 20kHz, 0.25VRMS input 0.25VRMS input, frequency where output is -3dB referenced to 1kHz No sustained oscillations; 75 series resistor on output 3.95 -1.5 Pulldown Resistance AUDIO CHARACTERISTICS Voltage Gain Gain Mismatch Flatness Frequency Bandwidth Capacitive Drive 4.4 7.5 4 0.006 230 300 4.05 +1.5 V/V % dB kHz pF 4 _______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors ELECTRICAL CHARACTERISTICS (continued) (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER Input Resistance Input Bias Current Input Signal Amplitude Output DC Level Power-Supply Rejection Ratio Signal-to-Noise Ratio Total Harmonic Distortion Plus Noise Output Impedance Volume Control Attenuation Step Volume Control Minimum Attenuation Volume Control Maximum Attenuation Mute Suppression Audio Crosstalk VIDEO-TO-AUDIO INTERACTION Crosstalk CHARGE PUMP Switching Frequency FAST SWITCHING Input Low Input High Level Input Current Output Low Voltage Output High Voltage Output Resistance Rise Time Fall Time SLOW SWITCHING Input Low Voltage Input Medium Voltage Input High Voltage 4.5 9.5 2 7 V V V 143 to GNDVID 143 to GNDVID TA = +25C IOL = 0.5mA IOH = 0.5mA VVID 0.1 7 12 10 1 10 0.1 0.4 V V A V V ns ns 570 kHz Video input: f = 15kHz, 1VP-P signal Audio input: f = 15kHz, 0.5VRMS signal 92 dB f = 1kHz, 0.25VRMS input f = 1kHz, 0.25VRMS input SYMBOL CONDITIONS VIN = -0.707V to +0.707V VIN = 0, TA = +25C f = 1kHz, THD < 1% No input signal, VIN grounded DC f = 1kHz f = 1kHz, 0.25VRMS input, 20Hz to 20kHz RL = 3.33k, f = 1kHz, 0.25VRMS input RL = 3.33k, f = 1kHz, 0.5VRMS input f = 1kHz Programmable gain to TV SCART volume control from -62dB to 0 -4 75 100 90 96 0.002 0.001 0.4 2 0 62 110 100 0.5 +4 MIN TYP 10 500 MAX UNITS M nA VRMS mV dB dB % dB dB dB dB dB MAX9670/MAX9671 _______________________________________________________________________________________ 5 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 ELECTRICAL CHARACTERISTICS (continued) (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER Input Current Output Low Voltage Output Medium Voltage Output High Voltage DIGITAL INTERFACE Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance 0.1VVID < SDA < 3.3V, 0.1VVID < SCL < 3.3V I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V+ is switched off, TA = +25C ISINK = 6mA VIH VIL VHYS IIH, IIL TA = +25C -1 6 0.06 x VVID +1 0.7 x VVID 0.3 x VVID V V V A pF 10k to EP, 11.4V V12 12.6V 10k to EP, 11.4V V12 12.6V 10k to EP, 11.4V V12 12.6V 5 10 SYMBOL CONDITIONS MIN TYP 70 MAX 100 1.5 6.5 UNITS A V V V Input Current -10 +10 A Output Low Voltage SDA Serial-Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time, (Repeated) START Condition Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Fall Time of SDA Transmitting Setup Time for STOP Condition Pulse Width of Spike Suppressed VOL fSCL tBUF tHD, STA tLOW tHIGH tSU, STA tHD, DAT tHD, DAT tF tSU, STO tSP 0.4 0 1.3 0.6 1.3 0.6 0.6 400 V kHz s s s s s (Note 5) ISINK 6mA, CB = total capacitance of one bus line in pF, tR and tF measured between 0.3VVID and 0.7VVID 0 100 100 0.6 0.9 s ns ns s Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns 0 50 ns 6 _______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors ELECTRICAL CHARACTERISTICS (continued) (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER OTHER DIGITAL I/O DEV_ADDR Low Level DEV_ADDR High Level DEV_ADDR Input Current Interrupt Output Low Voltage Interrupt Output Leakage Current TA = +25C IOL = 0.5mA INT high impedance, TA = +25C 0.7 x VVID -1 +1 0.1 10 0.3 x VVID V V A V A SYMBOL CONDITIONS MIN TYP MAX UNITS MAX9670/MAX9671 Note 2: Note 3: Note 4: Note 5: All devices are 100% production tested at TA = +25C. Specifications over temperature limits are guaranteed by design. Normal operation mode is full power with input video and load detection active. The settling time is measured from the 50% of the input swing to the 0.1% of the final value of the output. A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL's falling edge. Typical Operating Characteristics (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.) SMALL-SIGNAL GAIN vs. FREQUENCY VOUT = 100mVP-P 0 -10 GAIN (dB) -20 FILTER -30 -40 -50 -60 100k 1M 10M FREQUENCY (Hz) 100M 1G NO FILTER GAIN (dB) MAX9670 toc01 SMALL-SIGNAL GAIN FLATNESS vs. FREQUENCY MAX9670 toc02 LARGE-SIGNAL GAIN vs. FREQUENCY VOUT = 2VP-P 0 -10 NO FILTER GAIN (dB) -20 FILTER -30 -40 -50 -60 MAX9670 toc03 10 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 1M 10M FREQUENCY (Hz) FILTER NO FILTER VOUT = 100mVP-P 10 100M 100k 1M 10M FREQUENCY (Hz) 100M 1G _______________________________________________________________________________________ 7 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Typical Operating Characteristics (continued) (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.) LARGE-SIGNAL GAIN FLATNESS vs. FREQUENCY MAX9670 toc04 VIDEO CROSSTALK vs. FREQUENCY MAX9670 toc05 GROUP DELAY vs. FREQUENCY VOUT = 2VP-P 120 100 DELAY (ns) 80 60 40 20 0 NO FILTER FILTER MAX9670 toc06 2 1 0 -1 GAIN (dB) -2 -3 -4 -5 -6 -7 -8 1M 10M FREQUENCY (Hz) FILTER NO FILTER 0 -20 -40 DELAY (ns) -60 -80 -100 -120 VOUT = 100mVP-P 140 ALL HOSTILE 100M 100k 1M 10M 100M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) VIDEO POWER-SUPPLY REJECTION RATIO vs. FREQUENCY -5 -10 -15 PSRR (dB) -20 -25 -30 -35 -40 -45 -50 100k 1M 10M 100M FREQUENCY (Hz) DIFFERENTIAL GAIN (%) 1.97 1.96 0 NO FILTER FILTER MAX9670 toc07 VIDEO VOLTAGE GAIN vs. TEMPERATURE MAX9670 toc08 VIDEO OUTPUT VOLTAGE vs. INPUT VOLTAGE MAX9670 toc09 0 2.04 2.03 VOLTAGE GAIN (V/V) 2.02 2.01 2.00 1.99 1.98 3.5 3.0 OUTPUT VOLTAGE (V) 2.5 2.0 1.5 1.0 0.5 0 25 50 75 0 0.4 0.8 INPUT VOLTAGE (V) 1.2 1.6 TEMPERATURE (C) DIFFERENTIAL GAIN AND PHASE DIFFERENTIAL GAIN (%) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 1 2 3 4 5 1 2 3 4 5 MAX9670 toc10 DIFFERENTIAL GAIN AND PHASE 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 1 2 3 4 5 1 2 3 4 5 MAX9670 toc11 2T WITH FILTER MAX9670 toc12 VIDEO INPUT 200mV/div DIFFERENTIAL PHASE (deg) DIFFERENTIAL PHASE (deg) VIDEO OUTPUT 500mV/div 80ns/div 8 _______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Typical Operating Characteristics (continued) (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.) 2T NO FILTER MAX9670 toc13 MAX9670/MAX9671 12.5T WITH FILTER MAX9670 toc14 VIDEO INPUT 200mV/div VIDEO INPUT 200mV/div VIDEO OUTPUT 500mV/div VIDEO OUTPUT 500mV/div 80ns/div 1s/div 12.5T NO FILTER MAX9670 toc15 NTC7 WITH FILTER MAX9670 toc16 VIDEO INPUT 200mV/div VIDEO INPUT 500mV/div VIDEO OUTPUT 500mV/div VIDEO OUTPUT 1V/div 1s/div 10s/div NTC7 NO FILTER MAX9670 toc17 FIELD SQUARE WAVE MAX9670 toc18 VIDEO INPUT 500mV/div VIDEO INPUT 500mV/div VIDEO OUTPUT 1V/div VIDEO OUTPUT 1V/div 10s/div 2ms/div _______________________________________________________________________________________ 9 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Typical Operating Characteristics (continued) (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.) VIDEO INPUT SYNC-TIP CLAMP VOLTAGE vs. TEMPERATURE MAX9670 toc19 VIDEO INPUT BIAS VOLTAGE vs. TEMPERATURE 615 INPUT BIAS VOLTAGE (mV) 610 605 600 595 590 585 580 MAX9670 toc20 2 1 INPUT CLAMP VOLTAGE (mV) 0 -1 -2 -3 -4 -5 -6 0 25 50 620 75 0 25 50 75 TEMPERATURE (C) TEMPERATURE (C) VIDEO INPUT SYNC-TIP CLAMP CURRENT vs. TEMPERATURE MAX9670 toc21 VIDEO INPUT SYNC-TIP CLAMP CURRENT vs. INPUT VOLTAGE 7 INPUT CLAMP CURRENT (A) 6 5 4 3 2 1 0 MAX9670 toc22 1.4 1.3 INPUT CLAMP CURRENT (mA) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0 25 50 8 75 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 TEMPERATURE (C) INPUT VOLTAGE (V) VIDEO OUTPUT BIAS VOLTAGE vs. TEMPERATURE MAX9670 toc23 AUDIO LARGE-SIGNAL GAIN vs. FREQUENCY MAX9670 toc24 1.50 1.49 OUTPUT BIAS VOLTAGE (V) 1.48 10 5 0 GAIN (dB) -5 -10 -15 -20 1.47 1.46 1.45 1.44 1.43 1.42 0 25 50 75 TEMPERATURE (C) 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Typical Operating Characteristics (continued) (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.) AUDIO CROSSTALK vs. FREQUENCY MAX9670 toc25 MAX9670/MAX9671 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY VIN = 0.25VRMS MAX9670 toc26 0 -20 CROSSTALK (dB) -40 0.1 0.01 THD+N (%) TVIN TO TVOUT -60 -80 -100 -120 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 TVIN TO VCROUT 0.0001 10 100 1k FREQUENCY (Hz) 10k 100k VAUD POWER-SUPPLY REJECTION RATIO (INPUT REFERRED) vs. FREQUENCY VAUD = 3.3V + 100mVP-P -20 -40 PSRR (dB) -60 -80 -100 -120 10 100 1k FREQUENCY (Hz) 10k 100k MAX9670 toc27 VVID QUIESCENT SUPPLY CURRENT vs. TEMPERATURE MAX9670 toc28 0 30 25 CURRENT (mA) 20 15 10 5 0 0 25 50 75 TEMPERATURE (C) VAUD QUIESCENT SUPPLY CURRENT vs. TEMPERATURE MAX9670 toc29 V12 QUIESCENT SUPPLY CURRENT vs. TEMPERATURE 700 600 CURRENT (nA) 500 400 300 200 100 MAX9670 toc30 5 800 4 CURRENT (mA) 3 2 1 0 0 25 50 75 TEMPERATURE (C) 0 0 25 50 75 TEMPERATURE (C) ______________________________________________________________________________________ 11 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Pin Description PIN MAX9670 1 2 3 MAX9671 1 2 3 NAME SDA SCL DEV_ADDR FUNCTION Bidirectional I2C Data I/O. Output is open drain and tolerates up to 3.6V. I2C Clock Input Device Address Set Input. Connect to GNDVID, VVID, SDA or SCL. See Table 3. Interrupt Output. This is an open-drain output that pulls down to GNDVID to indicate a change in the VCR slow switching or fast switching input, the activity status of the composite video inputs, or the load status of the composite video outputs. Audio Supply. Connect to a 3.3V supply. Bypass with a 10F aluminum electrolytic capacitor and a 0.47F ceramic capacitor to EP. Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.47F capacitor from C1P to C1N. Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.47F capacitor from C1P to C1N. Charge-Pump Negative Power Supply. Bypass with a 1F ceramic capacitor to EP. Encoder Left-Channel Audio Input Encoder Right-Channel Audio Input TV SCART Left-Channel Audio Input TV SCART Right-Channel Audio Input VCR SCART Left-Channel Audio Input VCR SCART Right-Channel Audio Input TV SCART Left-Channel Audio Output VCR SCART Left-Channel Audio Output VCR SCART Right-Channel Audio Output TV SCART Right-Channel Audio Output TV SCART Bidirectional Slow-Switch Signal +12V Supply for the Slow Switching Circuit. Bypass with a 10F + 0.47F ceramic capacitor to EP. VCR SCART Bidirectional Slow-Switch Signal TV SCART Fast-Switching Logic Output No Connection. Leave unconnected. VCR SCART Fast-Switching Logic Input Encoder Blue Video Input Encoder Green Video Input VCR SCART Blue Video Input VCR SCART Green Video Input TV SCART Blue Video Output TV SCART Green Video Output 4 4 INT 5 6 7 8 9 10 -- -- 11 12 13 14 15 16 17 18 19 20 -- 21 22 23 24 25 26 27 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23, 44 24 25 26 27 28 29 30 VAUD C1P C1N CPVSS ENC_INL ENC_INR TV_INL TV_INR VCR_INL VCR_INR TV_OUTL VCR_OUTL VCR_OUTR TV_OUTR TV_SS V12 VCR_SS TVOUT_FS N.C. VCRIN_FS ENC_B_IN ENC_G_IN VCR_B_IN VCR_G_IN TV_B_OUT TV_G_OUT 12 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Pin Description (continued) PIN MAX9670 28 29 30 31 32 33 34 35 36 37 38 39 40 -- MAX9671 31 32 33 34 35 36 37 38 39 40 41 42 43 -- NAME GNDVID VCR_R/C_IN VVID ENC_C_IN ENC_R/C_IN TV_R/C_OUT VCR_R/C_OUT TV_Y/CVBS_OUT VCR_Y/CVBS_IN TV_Y/CVBS_IN ENC_Y_IN ENC_Y/CVBS_IN EP Video Ground VCR SCART Red/Chroma Video Input Video and Digital Supply. Connect to a 3.3V supply. Bypass with parallel 1F and 0.1F ceramic capacitors to GNDVID. VVID also serves as a digital supply for the I2C interface. Encoder Chroma Video Input Encoder Red/Chroma Video Input TV SCART Red/Chroma Video Output VCR SCART Red/Chroma Video Output TV SCART Luma/Composite Video Output VCR SCART Luma/Composite Video Input TV SCART Luma/Composite Video Input Encoder Luma Video Input Encoder Luma/Composite Video Input Exposed Pad. The exposed pad is the internal ground for the audio amplifiers and charge pump. A low-impedance connection between ground and EP is required for proper isolation. FUNCTION MAX9670/MAX9671 VCR_Y/CVBS_OUT VCR SCART Luma/Composite Video Output Detailed Description The MAX9670/MAX9671 represents Maxim's third generation of SCART audio/video (A/V) switches. Under I2C control, these devices route audio, video, and control information between the set-top box decoder chip and two SCART connectors. The audio signals are left audio and right audio. The video signals are composite video with blanking and sync (CVBS) and component video (red, green, blue). S-video (Y/C) can be transported across the SCART interface if CVBS is reassigned to luma (Y) and red is reassigned to chroma (C). Support for S-video is optional. The slow-switch signal and the fast-switch signal carry control information. The slowswitch signal is a 12V, three-level signal that indicates whether the picture aspect ratio is 4:3 or 16:9 or causes the television to use an internal A/V source such as an antenna. The fast-switch signal indicates whether the television should display CVBS or RGB signals. CVBS, left audio, and right audio are full duplex. All the other signals are half duplex. Therefore, one device on the link must be designated as the transmitter, and the other device must be designated as the receiver. The low power consumption and the advanced monitoring functions of the MAX9670/MAX9671 enable the cre- ation of lower power set-top boxes, televisions, and DVD players. Unlike competing SCART ICs, the audio and video circuits of the MAX9670/MAX9671 operate entirely from 3.3V rather than from 5V and 12V. Only the slow-switch circuit of the MAX9670/MAX9671 requires a 12V supply. The MAX9670/MAX9671 also have circuits that detect activity on the CVBS inputs, loads on the CVBS outputs, and the level of the slow-switch signals. The INT signal informs the microcontroller if there are any changes so that the microcontroller can intelligently decide whether to power up or power down the equipment. In addition, the MAX9670/MAX9671 have DirectDrive audio circuitry to eliminate click-and-pop noise. With DirectDrive, the DC bias of the audio line outputs is always at ground, no matter whether the MAX9670/ MAX9671 are being powered up or powered down. Conventional audio line output drivers that operate from a single supply require series AC-coupling capacitors. During power-up, the DC bias on the AC-coupling capacitor moves from ground to a positive voltage, and during power-down, the opposite occurs. The changing DC bias usually causes an audible transient. ______________________________________________________________________________________ 13 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 ZCD MUTE ENC_INL MUTE VCR_INL (0.5VRMS FULL-SCALE INPUT) VOLUME CONTROL 0dB TO -62dB MUTE VOLUME CONTROL 0dB TO -62dB MUTE x4 TV_OUTL (2VRMS FULL-SCALE OUTPUT) TV_OUTR x4 *TV_INL x4 MUTE ENC_INR (2VRMS FULL-SCALE OUTPUT) VCR_INR MUTE *TV_INR SCL SDA DEV_ADDR REGISTER CONTROL VCR_OUTL x4 VCR_OUTR VAUD C1P EP C1N CPVSS *MAX9671 ONLY. CHARGE PUMP MAX9670/MAX9671 Figure 1. MAX9670/MAX9671 Audio Section Functional Diagram Audio Section The MAX9670 audio circuit is essentially a stereo, 2-by-2, nonblocking, audio crosspoint with output drivers. The encoder (stereo audio DAC) and the VCR are the two input sources, and the two outputs go to the TV SCART connector and the VCR SCART connector. See Figure 1. The MAX9671 audio circuit is similar to that of the MAX9670 except that it is a stereo, 3-by-2, nonblocking audio crosspoint with TV as the third input source. The integrated charge pump inverts the +3.3V supply to create a -3.3V supply. The audio circuit operates from bipolar supplies so the audio signal is always biased to ground. 14 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Audio Outputs The MAX9670/MAX9671 audio output amplifiers feature Maxim's patented DirectDrive architecture, thereby eliminating the need for output-coupling capacitors required by conventional single-supply audio line drivers. An internal charge pump inverts the positive supply (VAUD), creating a negative supply (CPVSS). The audio output amplifiers operate from these bipolar supplies with their outputs biased about audio ground (Figure 2). The benefit of this audio ground bias is that the amplifier outputs do not have a DC component. The DC-blocking capacitors required with conventional audio line drivers are unnecessary, conserving board space, reducing system cost, and improving frequency response. Conventional single-supply audio line drivers have their outputs biased about a nominal DC voltage (typically half the supply) for maximum dynamic range. Large coupling capacitors are needed to block this DC bias. Clicks and pops are created when the coupling capacitors are charged during power-up and discharged during power-down. The MAX9670/MAX9671 features a low-noise charge pump that requires only two small ceramic capacitors. The 580kHz switching frequency is well beyond the audio range and does not interfere with audio signals. The switch drivers feature a controlled switching speed that minimizes noise generated by turn-on and turn-off transients. The SCART standard specifies 2VRMS as the full-scale for audio signals. As the audio circuits process 0.5V RMS full-scale audio signals internal to the MAX9670/MAX9671, the gain-of-4 output amplifiers restore the audio signals to a full-scale of 2VRMS. To select which audio input source is routed to the TV SCART connector, write to bits 1 and 0 of the TV Audio Control register (01h). To select which audio input source is routed to the VCR SCART connector, write to bits 3 and 2 of the TV Audio Control register (01h). The power-on default is for the TV and VCR audio outputs to be muted (the inputs of the output amplifiers are connected to audio ground). See Tables 10 and 13. MAX9670/MAX9671 VDD VDD/2 GND VDD CONVENTIONAL DRIVER-BIASING SCHEME +VDD GND VOUT 2VDD -VDD DirectDrive BIASING SCHEME Figure 2. Conventional Driver Output Waveform vs. MAX9670/ MAX9671 Output Waveform. Clickless Switching The TV audio channel incorporates a zero-crossing detect (ZCD) circuit that minimizes click noise due to abrupt signal level changes that occur when switching between audio signals at an arbitrary moment. To implement the zero-crossing function when switching audio signals, set the ZCD bit high (Audio Control register 00h, bit 6). Then set the mute bit high (Audio Control register 00h, bit 0). Next, wait for a sufficient period of time for the audio signal to cross zero. This period is a function of the audio signal path's low-frequency 3dB corner (fL3dB). Thus, if fL3dB = 20Hz, the time period to wait for a zero-crossing detect is 1/20Hz or 50ms. After the wait period, select a new audio source for the TV audio channel by writing to bits 1 and 0 of TV Audio Control register (01h). Finally, clear mute (Audio Control register, 00h, bit 0), but leave ZCD (Audio Control register 00h, bit 6) high. The MAX9670/MAX9671 switches the signal out of mute at the next zero crossing. See Tables 12 and 13. Volume Control Volume control is programmable from -62dB to 0dB in 2dB steps through I2C interface. The block consists of a resistive ladder network to generate 31 2dB volume control steps, a unity gain buffer to isolate the input from the resistive ladder, switches (MPLx and MNLx) that select 1 of 32 nodes on the resistive ladder, and logic to decode the the I2C volume control value. See Table 12. 15 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 ACTIVITY DETECT ACTIVITY DETECT ACTIVITY DETECT ACTIVITY DETECT TV_Y/CVBS_IN VCR_Y/CVBS_IN ENC_Y/CVBS_IN ENC_Y_IN CLAMP CLAMP AV = 2V/V CLAMP CLAMP MUTE LOAD SENSE AV = 2V/V VCR_Y/CVBS_OUT LPF LPF TV_Y/CVBS_OUT LOAD SENSE MAX9670/MAX9671 VCR_R/C_IN ENC_R/C_IN ENC_C_IN CLAMP/BIAS AV = 2V/V CLAMP/BIAS CLAMP/BIAS MUTE AV = 2V/V VCR_R/C_OUT LPF LPF TV_R/C_OUT VCR_G_IN ENC_G_IN CLAMP AV = 2V/V CLAMP MUTE LPF TV_G_OUT VCR_B_IN ENC_B_IN CLAMP AV = 2V/V CLAMP MUTE VVID AV = 1V/V GNDVID TVOUT_FS LPF TV_B_OUT VCRIN_FS 0.7V V12 AV = 1V/V +6V EP TO I2C x1 V12 AV = 1V/V +6V EP TO I2C x1 VCR_SS TV_SS Figure 3. MAX9670/MAX9671 Video Section Function Diagram Video Section The video circuit routes different video formats between the set-top box decoder, the TV SCART connector, and 16 the VCR SCART connector. It also routes slow-switch and fast-switch control information. See Figure 3. ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Video Inputs Whether the incoming video signal is AC-coupled or DC-coupled into the MAX9670/MAX9671 depends upon the origin, format, and voltage range of the video signal. Table 1 below shows the recommended connections. Always AC-couple an external video signal through a 0.1F capacitor because its voltage is not well defined (see the Typical Application Circuit). For example, the video transmitter circuit might have a different ground than the video receiver, thereby level shifting the DC bias. 60Hz power line hum might cause the video signal to change DC bias slowly. Internal video signals that are between 0 and 1V can be DC-coupled. Most video DACs generate video signals between 0 and 1V because the video DAC sources current into a ground-referenced resistor. For the minority of video DACs that generate video signals between 2.3V and 3.3V because the video DAC sinks current from a VVID-referenced resistor, AC-couple the video signal to the MAX9670/MAX9671. The MAX9670/MAX9671 restore the DC level of incoming, AC-coupled video signals with either transparent sync-tip clamps or bias circuits. When using an ACcoupled input, the transparent sync-tip clamp automatically clamps the input signal minimum to ground, preventing it from going lower. A small current of 1A pulls down on the input to prevent an AC-coupled signal from drifting outside the input range of the part. Use sync-tip clamps with CVBS, RGB, and luma signals. The transparent sync-tip clamp is transparent when the incoming video signal is DC-coupled and at or above ground. Under such conditions, the clamp never activates. Therefore, the outputs of video DACs that generate signals between 0 and 1V can be directly connected to the MAX9670/MAX9671 inputs. The bias circuit accepts AC-coupled chroma, which is a subcarrier with the color information modulated onto it. The bias voltage of the bias circuits is around 600mV. ENC_R/C_IN and VCR_R/C_IN can receive either a red video signal or a chroma video signal. Set the input configuration by writing to bits 7 and 3 of the VCR Video Input Control register (08h). See Tables 10 and 16. The MAX9670/MAX9671 also have video input detection. When activated, activity detect circuits check if sync is present on incoming CVBS and luma (Y) signals. If so, then there is a valid video signal. Read bits 0, 2, 4, and 5 of the Video Activity Status register (0Fh) to determine the status of the CVBS and luma (Y) inputs. See Table 21. In high-impedance mode, the inputs to the MAX9670/ MAX9671 do not distort the video signal in case the outputs of the video DAC are also connected to another video circuit such as a high-definition video filter amplifier. See the SCART Set-Top Box with Analog HD Outputs section. The inputs in high-impedance mode are biased at VVID/3, which is sufficiently above ground so that the ESD diodes never forward biases as the video signal changes. The input resistance is 222k, which presents negligible loading on the video current DAC. MAX9670/MAX9671 Video Reconstruction Filter The video DAC outputs of the set-top box decoder chip need to be lowpass-filtered to reject the out-of-band noise. The MAX9670/MAX9671 integrate sixth-order, Butterworth filters. The filter passband (1dB) is typically 5.5MHz, and the attenuation at 27MHz is 52dB. The filters are suited for standard-definition video. Video Outputs The video output amplifiers can both source and sink load current, allowing output loads to be DC- or ACcoupled. The amplifier output stage needs around 300mV of headroom from either supply rail. For video signals with a sync pulse, the sync tip is typically at 300mV, as shown in Figure 4. For a chroma signal, the blank level is typically at 1.5V, as shown in Figure 5. If the supply voltage is greater than 3.135V (5% below a 3.3V supply), each amplifier can drive two DC-coupled video loads to ground. If the supply is less than 3.135V, each amplifier can drive only one DC-coupled or AC-coupled video load. The SCART standard allows for video signals to have a superimposed DC component within 0 and 2V. Therefore, most video signals are DC-coupled at the output. In the unlikely event that the video signal needs to be AC-coupled, the coupling capacitors should be 220F or greater to keep the highpass filter formed by the 37.5 equivalent resistance of the video transmission line to a corner frequency of 4.8Hz or below to keep it well below the 25Hz frame rate of the PAL standard. The CVBS outputs have load sense circuits. If enabled, each load sense circuit checks for a load eight times per second by connecting an internal 15k pullup resistor to the output for 1ms. If the output is pulled up, no load is present. If the output stays low, a load is connected. Read bits 1 and 3 of the Video Activity Status register (0Fh) to determine load status. See Table 21. The selection of video sources that are sent to the TV SCART connector are controlled by bits 0 to 4 of the TV Video Input Control register (06h) while the selection of ______________________________________________________________________________________ 17 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 video sources that are sent to the VCR SCART connector are controlled by bits 0 to 2 of the VCR Video Input Control register (08h). See Tables 10, 14, and 16. The video outputs can be enabled or disabled by bits 2 through 7 of the Output Enable register (0Dh). See Table 18. the fast-switching signal is just used to switch between CVBS and RGB signal sources. Set the source of the fast-switching signal by writing to bits 4 and 3 of the TV Video Output Control register (07h). The fast-switching signal to the TV SCART connector can be enabled or disabled by bit 1 of the Output Enable register (0Dh). See Tables 10, 15, and 18. Slow Switching The MAX9670/MAX9671 support the IEC 933-1, Amendment 1, three-level slow switching that selects the aspect ratio for the display (TV). Under I2C control, the MAX9670/MAX9671 set the slow-switching output voltage level. Table 2 shows the valid input levels of the slow-switching signal and the corresponding operating modes of the display device. Two bidirectional ports are available for slow-switching signals for the TV and VCR. The slow-switching input status is continuously read and stored in the Status register (0Eh). The slow-switching outputs can be set to a logic level or high impedance by writing to the TV Video Output Control register (07h) and the VCR Video Output Control register (09h). When enabled, INT becomes active low if the voltage level changes on TV_SS or VCR_SS. See Tables 10, 15, 17, and 20. I2C Serial Interface The MAX9670/MAX9671 feature an I2C/SMBusTM-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9670/ MAX9671 and the master at clock rates up to 400kHz. Figure 6 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. A master device writes data to the MAX9670/ MAX9671 by transmitting a START (S) condition, the proper slave address with the R/W bit set to 0, followed by the register address and then the data word. Each transmit sequence is framed by a START and a STOP (P) condition. Each word transmitted to the MAX9670/MAX9671 is 8 bits long and is followed by an acknowledge clock pulse. A master reads from the MAX9670/MAX9671 by transmitting the slave address with the R/W bit set to 0, the register address of the register to be read, a REPEATED START (Sr) condition, the slave address with the R/W bit set to 1, followed by a series of SCL pulses. The MAX9670/MAX9671 transmit data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or Fast Switching The fast-switching signal was originally used to switch between CVBS and RGB signals on a pixel-by-pixel basis so that on-screen display (OSD) information could be inserted. Since modern set-top box decoder chips have integrated OSD circuitry, there is no need to create OSD information using the older technique. Now, MAX9670 fig04 MAX9670 fig05 INPUT 500mV/div INPUT 200mV/div OUTPUT 500mV/div OUTPUT 200mV/div 20s/div 10s/div Figure 4. MAX9670/MAX9671 Video Output with CVBS Signal, Multiburst Video Test Signal Shown Figure 5. MAX9670/MAX9671 Video Output with Chroma (C) Signal, Multiburst Video Test Signal Shown 18 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tBUF tHD, STA tSP tSU, STO Figure 6. I2C Serial-Interface Timing Diagram REPEATED START condition, an acknowledge or a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500, is required on the SDA bus. SCL operates as only an input. A pullup resistor, typically greater than 500, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9670/MAX9671 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. S Sr P SCL SDA Figure 7. START, STOP, and REPEATED START Conditions Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-tohigh transition on SDA while SCL is high (Figure 7). A START condition from the master signals the beginning of a transmission to the MAX9670/MAX9671. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The MAX9670/MAX9671 recognize a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The slave address is defined as the 7 most significant bits (MSBs) followed by the read/write (R/W) bit. Set the R/W bit to 1 to configure the MAX9670/MAX9671 to read mode. Set the R/W bit to 0 to configure the MAX9670/MAX9671 to write mode. The slave address is always the first byte of information sent to the MAX9670/MAX9671 after a START or a REPEATED START condition. The MAX9670/MAX9671 slave address is configurable with DEV_ADDR. Table 3 shows the possible slave addresses for the MAX9670/MAX9671. ______________________________________________________________________________________ 19 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9670/MAX9671 use to handshake receipt of each byte of data when in write mode (see Figure 8). The MAX9670/MAX9671 pull down SDA during the entire master-generated ninth clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when CLOCK PULSE FOR ACKNOWLEDGMENT the MAX9670/MAX9671 are in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9670/MAX9671, followed by a STOP condition. Write Data Format A write to the MAX9670/MAX9671 consists of transmitting a START condition, the slave address with the R/W bit set to 0, one data byte to configure the internal register address pointer, one or more data bytes, and a STOP condition. Figure 9 illustrates the proper frame format for writing one byte of data to the MAX9670/MAX9671. Figure 10 illustrates the frame format for writing n bytes of data to the MAX9670/ MAX9671. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9670/ MAX9671. The MAX9670/MAX9671 acknowledge receipt of the address byte during the master-generated ninth SCL pulse. The second byte transmitted from the master configures the MAX9670/MAX9671's internal register address pointer. The pointer tells the MAX9670/MAX9671 where to write the next byte of data. An acknowledge pulse is sent by the MAX9670/MAX9671 upon receipt of the address pointer data. START CONDITION SCL 1 2 8 NOT ACKNOWLEDGE 9 SDA ACKNOWLEDGE Figure 8. Acknowledge ACKNOWLEDGE FROM MAX9670/MAX9671 B7 ACKNOWLEDGE FROM MAX9670/MAX9671 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9670/MAX9671 REGISTER ADDRESS A DATA BYTE 1 BYTE A P B6 B5 B4 B3 B2 B1 B0 Figure 9. Writing a Byte of Data to the MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 S SLAVE ADDRESS R/W 0 A REGISTER ADDRESS A B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9670/MAX9671 B7 B6 B5 B4 B3 B2 B1 B0 DATA BYTE 1 1 BYTE A DATA BYTE n 1 BYTE A P AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 10. Writing n Bytes of Data to the MAX9670/MAX9671 20 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9670/MAX9671 REGISTER ADDRESS A Sr ACKNOWLEDGE FROM MAX9670/MAX9671 SLAVE ADDRESS R/W 1 NOT ACKNOWLEDGE FROM MASTER A DATA BYTE 1 BYTE A P REPEATED START AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 11. Reading One Indexed Byte of Data from the MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9670/MAX9671 REGISTER ADDRESS A Sr ACKNOWLEDGE FROM MAX9670/MAX9671 SLAVE ADDRESS R/W 1 A NOT ACKNOWLEDGE FROM MASTER DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P REPEATED START Figure 12. Reading n Bytes of Indexed Data from the MAX9670/MAX9671 The third byte sent to the MAX9670/MAX9671 contains the data that is written to the chosen register. An acknowledge pulse from the MAX9670/MAX9671 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential register address locations within one continuous frame. The master signals the end of transmission by issuing a STOP condition. addresses higher than 01h results in repeated reads from a dummy register containing FFh data. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figures 11 and 12 illustrate the frame format for reading data from the MAX9670/MAX9671. Read Data Format The master presets the address pointer by first sending the MAX9670/MAX9671's slave address with the R/W bit set to 0 followed by the register address after a START condition. The MAX9670/MAX9671 acknowledges receipt of its slave address and the register address by pulling SDA low during the ninth SCL clock pulse. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9670/MAX9671 transmits the contents of the specified register. Transmitted data is valid on the rising edge of the master-generated serial clock (SCL). The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from the register address location set by the previous transaction and not 00h and subsequent reads autoincrement the address pointer until the next STOP condition. Attempting to read from register Interrupt Output When interrupt is enabled in modes 1 and 2, INT, which is an open-drain output, pulls low under the following conditions: slow-switch signals change value, CVBS input signals are detected or disappear, and CVBS output loads are added or removed. When interrupt is enabled in mode 3, INT pulls low only when the slow-switch signal changes value. Enable INT by writing a 1 into bit 4 of register 01h. See Table 13. The interrupt can be cleared by reading register 0Eh and 0Fh. Applications Information Audio Inputs The maximum full-scale audio signal that can be applied to the audio inputs is 0.5V RMS biased at ground. The recommended application circuit to attenuate and bias an incoming audio signal is shown in Figure 13. 21 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors STEREO AUDIO DACS 1F 6.65k ENC_INL R1* 1F 6.65k ENC_INR R1* MAX9670 *R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53k, 1% DAC = PCM1742: R1 = 5.57k, 1% Figure 13. Application circuit to connect audio source to audio inputs. The 1F capacitor connected to the ground-referenced resistors biases the audio signal at ground. The resistors attenuate the audio signal. considers this condition to be illegal and does not loop through any signals. A finite state machine (Figure 14) controls the operation of the MAX9670/MAX9671. State 0 is always the initial state when the MAX9670/MAX9671 enter standby mode. Table 4 shows the values of the I2C registers in state 0. The state machine sets the other I2C registers to the correct values to loop through the audio/video signals in states 1 and 2 (see Tables 5 and 6). When the MAX9670/MAX9671 leaves standby mode, the values in all of the I2C registers except register 10h are preserved so that the operation is not disturbed. For example, if in standby mode, the MAX9670 is looping through the audio/video signals from VCR SCART to TV SCART, and if the microcontroller changes the operating mode from standby mode to full-power mode, the audio/video signals continue to be looped through during and after the mode change. The user does not experience any disruption in audio or video service. The microcontroller can be turned off in standby mode because the MAX9670/MAX9671 operate autonomously. Upon power-up, the default operating mode is standby mode. MAX9670/MAX9671 The audio path has a gain of 4V/V so that the full scale of the audio output signal is 2VRMS. If less than 2VRMS, full scale is desired at the audio outputs, and the full scale of the audio input signal should be proportionately decreased below 0.5VRMS. Operating Modes The MAX9670/MAX9671 has four operating modes, which can be set by writing to bits 6 and 7 of register 10h. See Table 19. Shutdown All circuitry is shutdown in the MAX9670/MAX9671 except for the I2C interface, which is designed with static CMOS logic. Except for register 10h, which sets the operating mode, the values in all of the other I2C registers are preserved while entering, during, and leaving shutdown mode. Standby Mode In standby mode, the MAX9670/MAX9671 monitor the slow-switch signals and decide whether to loop through the audio/video signals. If the VCR slow switch input has activity (6V or 12V at the input), the audio/video signals are looped through from the VCR SCART to the TV SCART. If the TV slow-switch input has activity, the audio/video signals are looped through from the TV SCART to the VCR SCART. If neither the VCR slowswitch input nor the TV slow switch input show activity, i.e., both inputs are at ground, no signals are looped through. If both the VCR slow-switch input and the TV slow-switch input have activity, the MAX9670/MAX9671 22 Full-Power Mode with Video Input Detection and Video Load Detection In this mode, the MAX9670/MAX9671 are fully on. If interrupt is enabled, INT goes active low whenever the slow-switch signal changes; a CVBS signal appears or disappears; or a CVBS load appears or disappears. The microcontroller can decide whether to change the routing configuration or operating mode of the MAX9670/MAX9671. Full-Power Mode Without Video Input Detection and Video Load Detection This mode is similar to the above mode except that video input detection and video load detection are not active. If interrupt is enabled, INT goes active low only when the slow-switch signal changes. Power Consumption The quiescent power consumption and average power consumption of the MAX9670/MAX9671 are very low because of 3.3V operation and low-power circuit design. Quiescent power consumption is defined when the MAX9670/MAX9671 are operating without loads and without any audio or video signals. Table 7 shows the quiescent power consumption in all 4 operating modes. Average power consumption is defined when the MAX9670/MAX9671 drives typical signals into typical loads. Table 8 shows the average power consumption ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 TV_SS NOT ACTIVE VCR_SS NOT ACTIVE TV_SS ACTIVE VCR_SS ACTIVE STATE 0 SEARCH AUDIO: INACTIVE VIDEO: INACTIVE SLOW SWITCH: LISTENING FOR ACTIVITY FAST SWITCH: INACTIVE TV_SS ACTIVE VCR_SS NOT ACTIVE TV_SS NOT ACTIVE VCR_SS ACTIVE TV_SS NOT ACTIVE VCR_SS NOT ACTIVE TV_SS NOT ACTIVE VCR_SS NOT ACTIVE TV_SS NOT ACTIVE VCR_SS ACTIVE TV_SS ACTIVE VCR_SS NOT ACTIVE STATE 1 TV-TO-VCR AUDIO: TV TO VCR VIDEO: TV TO VCR SLOW SWITCH: TV TO VCR FAST SWITCH: NOT APPLICABLE STATE 2 VCR-TO-TV AUDIO: VCR TO TV VIDEO: VCR TO TV SLOW SWITCH: VCR TO TV FAST SWITCH: VCR TO TV TV_SS ACTIVE VCR_SS ACTIVE TV_SS ACTIVE VCR_SS ACTIVE TV_SS ACTIVE VCR_SS NOT ACTIVE TV_SS NOT ACTIVE VCR_SS ACTIVE Figure 14. Standby mode finite state machine. TV_SS is active when either 6V or 12V are present. VCR_SS is active when either 6V or 12V are present. S-Video The MAX9670/MAX9671 support S-video from the settop box to the TV, set-top box to the VCR, and VCR to the set-top box. S-video was not included in the original SCART specifications but was added afterwards. As a consequence, the luma (Y) signal of S-video shares the same SCART pin as the CVBS signal. Likewise, the chroma (C) signal shares the same SCART pin as the red signal. The pins that can carry both CVBS and luma have Y/CVBS in their names, and the pins that can carry red and chroma have R/C in their names. Now, the Y/CVBS signals are full duplex while the R/C signals are half duplex. Therefore, S-video is limited to being half duplex. The MAX9670/MAX9671 have to transmit a chroma signal and receive a chroma signal ______________________________________________________________________________________ 23 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 0.1F VCR_R/C_IN ENC_R/C_IN ENC_C_IN BIAS AV = 2V/V BIAS BIAS LPF LPF TV_R/C_OUT 75 TV SCART AV = 2V/V VCR_R/C_OUT 75 MAX9670/MAX9671 ON VCR SCART Figure 15. Gain-of-2 amplifier on VCR_R/C_OUT outputs chroma signal to VCR SCART connector. Notice that the pulldown switch on VCR_R/C_OUT is open. 0.1F VCR_R/C_IN ENC_R/C_IN ENC_C_IN BIAS AV = 2V/V BIAS BIAS LPF LPF TV_R/C_OUT 75 TV SCART AV = 2V/V VCR_R/C_OUT 75 MAX9670/MAX9671 OFF VCR SCART Figure 16. VCR_R/C_IN receives chroma signal from VCR SCART connector. Notice that the pulldown switch on VCR_R/C_OUT is closed and that the gain-of-2 amplifier is off. The chroma signal from VCR SCART is looped through to the TV SCART in the above configuration. Now, the Y/CVBS signals are full duplex while the R/C signals are half duplex. Therefore, S-video is limited to being half duplex. The MAX9670/MAX9671 have to transmit a chroma signal and receive a chroma signal on the same SCART pin, but not at the same time. The 75 resistor connected to VCR_R/C_OUT must act as a back termination resistor when the MAX9670/MAX9671 is transmitting chroma signal and as an input termination resistor when it is receiving a chroma signal. Figure 15 shows how the MAX9670/MAX9671 transmits a 24 chroma signal to the VCR SCART connector while Figure 16 shows how the MAX9670/MAX9671 receives a chroma from the VCR SCART connector. Write a 0 into bit 2 of register 09h to open the pulldown switch at VCR_R/C_OUT. To close the pulldown switch, write a 0 into bit 6 of register 0Dh to turn off the output amplifier, and then write a 1 into bit 2 of register 09h. See Tables 17 and 18. ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 TV_OUTR 10k MAX9670/MAX9671 MONO AUDIO 10k TV_OUTL 75 TV_Y/CVBS_OUT 75 OR GREATER TV SCART 75 OR GREATER RF MODULATOR Figure 17. Application Circuit to Connect CVBS and Mono Audio from TV SCART to RF Modulator Interfacing to an RF Modulator If the set-top box modulates CVBS and mono audio onto an RF carrier (for example, channel 3), a simple application circuit can provide the needed signals (see Figure 17). 10k resistor summer circuit between TV_OUTR and TV_OUTL creates the mono audio signal. The resistor-divider to ground on TV_Y/CVBS_OUT creates a video signal with normal amplitude. The unique feature of the MAX9670/MAX9671 that facilitates this application circuit is that the audio and video output amplifiers of the MAX9670/MAX9671 can drive multiple loads if V AUD and V VID are both greater than 3.135V. To better protect the MAX9670/MAX9671 against excess voltages during the cable discharge condition or ESD events, add series resistors to all inputs and outputs to the SCART connector if series resistors are not already present in the application circuit. Also, add external ESD protection diodes (for example, BAV99) on all inputs and outputs to the SCART connector. SCART Set-Top Box with Analog HD Outputs In set-top boxes with SCART connectors and cinch connectors for high-definition YPbPr outputs, a triplevideo DAC usually outputs either standard-definition RGB signals that are routed to the MAX9670/MAX9671 or high-definition YPbPr signals that are routed through a high-definition filter amplifier like the MAX9653 (see Figure 19). The set-top box devices have a limited number of video DACs, and hence, one bank of triple-video DACs switches video format depending upon whether standard-definition RGB or high-definition YPbPr signals are required. When RGB signals are desired, the high-definition filter amplifier should be turned off so that the RGB signals do not appear on the YPbPr connectors. The MAX9653/MAX9654 are well-suited for this application because their video inputs are in high-impedance mode when in shutdown. Unconnected-Chassis Discharge Protection and ESD Some set-top boxes are not connected to earth ground. As a result, the chassis can charge up to 500V. When a SCART cable is connected to the SCART connector, the charged chassis can discharge through a signal pin. The equivalent circuit is a 2200pF capacitor charged to 311V connected through less than 0.1 to a signal pin. The MAX9670/MAX9671 are soldered on the PCB when it experiences such a discharge. Therefore, the current spike flows through both external and internal ESD protection devices and is absorbed by the supply bypass capacitors, which have high capacitance and low ESR. ______________________________________________________________________________________ 25 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 12V 0.1F 3.3V 0.1F 3.3V 0.1F VAUD 7.68k 1F V12 VVID VAUD TV_INL (MAX9671 ONLY) +3.3 V STB CHIP TV_INR (MAX9671 ONLY) 2.55k 7.68k VAUD CPVSS 1F MICROCONTROLLER SDA SCL INT DEV_ADDR 2.55k 75 TV_OUTR CPVSS VAUD VAUD 75 TV_OUTL 75 TV_SS 75 EP VVID 75 TV_G_OUT 75 TV_R/C_OUT 75 GNDVID VVID GNDVID VVID GNDVID VVID TV_Y/CVBS_IN 75 0.1F GNDVID GNDVID VVID CPVSS V12 CPVSS VVID VIDEO ENCODER 75 ENC_Y/CVBS_IN 75 75 ENC_R/C_IN 75 75 ENC_G_IN 75 75 ENC_B_IN 75 75 ENC_Y_IN 75 75 ENC_C_IN 75 TV_B_OUT TV SCART TVOUT_FS 75 TV_Y/CVBS_OUT MAX9670 MAX9671 GNDVID 75 VCR_OUTR GNDVID 75 VAUD VAUD 7.68k VCR_INR CPVSS 1F STEREO AUDIO DACS 1F 6.65k ENC_INL VCR_OUTL 2.55k 75 CPVSS VAUD VAUD 7.68k CPVSS 1F R1* VCR_INL 2.55k 75 ENC_INR VCR_SS VVID 75 0.1F EP CPVSS V12 VCR SCART 1F 6.65k R1* VCR_B_IN GNDVID VVID 75 VCR_G_IN VVID GNDVID 0.1F 75 0.1F 75 75 VCR_R/C_IN VVID GNDVID 75 VVID GNDVID VCR_R/C_OUT *R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53k 1% DAC = PCM1742: R1 = 5.57k 1% VCRIN_FS 75 VCR_Y/CVBS_OUT 75 VCR_Y/CVBS_IN 75 1F 1F GNDVID 75 VVID 0.1F C1P EP C1N CPVSS GNDVID VVID GNDVID Figure 18. Application Circuit to Connect Series Resistors and External ESD Protection Diodes at MAX9670/MAX9671 Outputs 26 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 0.1F 0.1F 3.3V SET-TOP BOX CHIP DAC 3.3V ENC_G_IN 0.1F ENC_B_IN TV_B_OUT TV_G_OUT 75 MAX9670/MAX9671 ENC_R/C_IN TV_R/C_OUT 75 SCART CONNECTOR SET-TOP BOX CHIP DAC 3.3V 0.1F 3.3V ENC_G_IN 0.1F ENC_B_IN TV_B_OUT TV_G_OUT 75 75 0.1F MAX9670/MAX9671 ENC_R/C_IN TV_R/C_OUT 75 SCART CONNECTOR 75 INPUTS SET TO SYNC-TIP CLAMP INPUTS SET TO HIGH IMPEDANCE DAC 3.3V DAC 3.3V DAC DAC MAX9653 MAX9654 YIN PBIN PRIN SHDN OFF (A) (B) YOUT 75 PBOUT 75 PROUT 3.3V YPbPr OUTPUTS 0.1F PRIN SHDN ON PROUT 0.1F PBIN PBOUT 75 75 0.1F YIN MAX9653 MAX9654 YOUT 75 YPbPr OUTPUTS 75 Figure 19. Triple DAC is connected to both a MAX9670/MAX9671 and a MAX9653/MAX9654 high-definition video-filter amplifier. (A) The MAX9670/MAX9671 are transmitting standard-definition RGB signals while the MAX9653/MAX9654 are in shutdown mode. (B) The MAX9670/MAX9671 are not transmitting RGB signals, but the MAX9653/MAX9654 are transmitting high-definition YPbPr signals. Similarly, when YPbPr signals are desired, ENC_R/C_IN, ENC_G_IN, and ENC_B_IN of the MAX9670/MAX9671 should be set to high-impedance mode by setting bit 4 in register 08h to high if those video inputs are AC-coupled. The high-impedance mode has higher priority whether ENC_R/C_IN is in sync-tip clamp or bias circuit mode (set by bit 3 in register 08h). If ENC_R/C_IN, ENC_G_IN, and ENC_B_IN are DC-coupled, the inputs should be left in sync-tip clamp mode. The RGB outputs of the MAX9670 should be muted or shut down. In either case, the inactive device should not distort the video signals generated by the DACs. and stripes appear on the television screen, increase the supply bypass capacitance. An additional, smaller capacitor in parallel with the main bypass capacitor can reduce digital supply noise because the smaller capacitor has lower equivalent series resistance (ESR) and equivalent series inductance (ESL). Layout and Grounding For optimal performance, use controlled-impedance traces for video signal paths and place input termination resistors and output back-termination resistors close to the MAX9670/MAX9671. Avoid routing video traces parallel to high-speed data lines. The MAX9670/MAX9671 provide separate ground connections for video and audio supplies. For best performance, use separate ground planes for each of the ground returns and connect all ground planes together at a single point. See the MAX9670/MAX9671 evaluation kit for a proven circuit board layout example. If the MAX9670/MAX9671 are mounted using flow soldering or wave soldering, the ground via(s) for the EP pad should have a finished hole size of at least 14mils to insure adequate wicking of soldering onto the exposed pad. If the MAX9670/MAX9671 are mounted using solder mask technique, the via requirement does not apply. In either case, a good connection between the exposed pad and ground is required to minimize noise from coupling onto the outputs. 27 Power-Supply Bypassing The MAX9670/MAX9671 feature single 3.3V and 12V supply operation and require no negative supply. The 12V supply V12 is for the SCART switching function. For V12, place a 0.1F bypass capacitor as close as possible. Connect all VAUD pins together to 3.3V and bypass with a 10F electrolytic capacitor in parallel with a 0.1F ceramic capacitor to audio ground. Bypass each VVID to video ground with a 0.1F ceramic capacitor. Using a Digital Supply The MAX9670/MAX9671 are designed to operate from noisy digital supplies. The high PSRR (49dB at 100kHz) allows the MAX9670/MAX9671 to reject the noise from the digital power supplies (see the Typical Operating Characteristics). If the digital power supply is very noisy ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Table 1. Recommended Coupling for Incoming Video Signals and Input Circuit Configuration* VIDEO ORIGIN External External External External Internal Internal Internal Internal Internal Internal Internal Internal FORMAT CVBS RGB Y C CVBS RGB Y/C YPbPr CVBS RGB Y C VOLTAGE RANGE Unknown Unknown Unknown Unknown 0 to 1V 0 to 1V 0 to 1V 0 to 1V 2.3V to 3.3V 2.3V to 3.3V 2.3V to 3.3V 2.3V to 3.3V COUPLING AC AC AC AC DC DC DC DC AC AC AC AC INPUT CIRCUIT CONFIGURATION Transparent sync-tip clamp Transparent sync-tip clamp Transparent sync-tip clamp Bias circuit Transparent sync-tip clamp Transparent sync-tip clamp Transparent sync-tip clamp Transparent sync-tip clamp Transparent sync-tip clamp Transparent sync-tip clamp Transparent sync-tip clamp Bias circuit *Use a 0.1F capacitor to AC-couple a video signal into the MAX9670/MAX9671. Table 2. Slow-Switching Modes SLOW-SWITCHING SIGNAL VOLTAGE (V) 0 to 2 MODE Display device uses an internal source such as a built-in tuner to provide a video signal. Display device uses a video signal from the SCART connector and sets the display to 16:9 aspect ratio. Display device uses a signal from the SCART connector and sets the display to 4:3 aspect ratio. 4.5 to 7.0 9.5 to 12.6 28 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Table 3. Slave Address DEV_ADDR GNDVID VVID SCL SDA B7 1 1 1 1 B6 0 0 0 0 B5 0 0 0 0 B4 1 1 1 1 B3 0 0 1 1 B2 1 1 0 0 B1 0 1 0 1 B0 R/W R/W R/W R/W WRITE ADDRESS (hex) 94h 96h 98h 9Ah READ ADDRESS (hex) 95h 97h 99h 9Bh MAX9670/MAX9671 Table 4. I2C Register Values in State 0* REGISTER ADDRESS (hexadecimal) 00h 01h 06h 07h 08h 09h 0Dh VALUE (binary) uuuu uuuu uuuu 1111 uuuu uuuu uuuu uu10 uuuu uuuu uuuu u010 0000 000u Table 5. I2C Register Values in State 1* REGISTER ADDRESS (hexadecimal) 00h 01h 06h 07h 08h 09h 0Dh VALUE (binary) uuuu uuu0 uuuu 1011 uuuu uuuu uuu0 0u10 uuuu u011 uuuu u0MM 1100 001u *u indicates that the bit is unchanged from its previous state. *u indicates that the bit is unchanged from its previous state; MM = Register 0Eh (bit 1, bit 0) Table 6. I2C Register Values in State 2* REGISTER ADDRESS (hexadecimal) 00h 01h 06h 07h 08h 09h 0Dh VALUE (binary) uuuu uuu0 uuuu 1101 uuu0 1010 uuu0 0uNN uuuu uuuu uuuu u110 0011 111u *u indicates that the bit is unchanged from its previous state; NN = Register 0Eh (bit 3, bit 2) ______________________________________________________________________________________ 29 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Table 7. Quiescent Power Consumption OPERATING MODE Shutdown Standby mode with no video activity (i.e., TV slow-switch and VCR slow-switch inputs are at ground). Standby mode is the power-on default. Full-power mode with input video detection and video load detection active. Full-power mode without input video detection and video load detection active. POWER CONSUMPTION (mW) 0.13 Table 8. Average Power Consumption OPERATING MODE Full-power mode with input video detection and video load detection active. Full-power mode without input video detection and video load detection active. POWER CONSUMPTION (mW) 300 2.83 300 66 65 Table 9. Conditions for Average Power Consumption Measurement PIN (MAX9670) 5 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NAME VAUD ENC_INL ENC_INR VCR_INL VCR_INR TV_OUTL VCR_OUTL VCR_OUTR TV_OUTR TV_SS V12 VCR_SS TVOUT_FS VCRIN_FS ENC_B_IN ENC_G_IN VCR_B_IN VCR_G_IN TV_B_OUT TV_G_OUT GNDVID VCR_R/C_IN VVID TYPE Supply Input Input Input Input Output Output Output Output Output Supply Input Output Input Input Input Input Input Output Output Supply Input Supply SIGNAL 3.3V 0.25VRMS, 1kHz 0.25VRMS, 1kHz None None 1VRMS, 1kHz 1VRMS, 1kHz 1VRMS, 1kHz 1VRMS, 1kHz 12V 12V 0 3.3V 0 50% flat field 50% flat field None None 50% flat field 50% flat field 0 None 3.3V LOAD N/A N/A N/A N/A N/A 10k to ground 10k to ground 10k to ground 10k to ground 10k to ground N/A N/A 150 to ground N/A N/A N/A N/A N/A 150 to ground 150 to ground N/A N/A N/A 30 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Table 9. Conditions for Average Power Consumption Measurement (continued) PIN (MAX9670) 31 32 33 34 35 36 37 38 39 40 NAME ENC_C_IN ENC_R/C_IN TV_R/C_OUT VCR_R/C_OUT VCR_Y/CVBS_OUT TV_Y/CVBS_OUT VCR_Y/CVBS_IN TV_Y/CVBS_IN ENC_Y_IN ENC_Y/CVBS_IN TYPE Input Input Output Output Output Output Input Input Input Input SIGNAL None 50% flat field 50% flat field 50% flat field 50% flat field 50% flat field None None None 50% flat field LOAD N/A N/A 150 to ground 150 to ground 150 to ground 150 to ground N/A N/A N/A N/A Table 10. Data Format for Write Mode REGISTER ADDRESS (hex) 00h 01h 02h 03h 04h 05h 06h 07h 08h VCR_R/C_IN clamp BIT 7 Not used BIT 6 TV ZCD Not used BIT 5 BIT 4 BIT 3 TV volume control BIT 2 BIT 1 BIT 0 TV audio output mute Not used Not used Not used 09h 0Ah 0Bh 0Ch 0Dh 10h VCR_Y/ VCR_R/ CVBS_OUT C_OUT enable enable Operating mode Not used TV_R/ C_OUT enable Interrupt VCR audio selection TV audio selection enable Not used Not used Not used Not used TV G and B video switch TV video switch Set TV fast switching Not used Set TV slow switching ENC R/G/B ENC_R/C_IN highVCR video switch clamp impedance bias VCR_R/C_OUT Set VCR slow ground switching Not used Not used Not used TV_Y/ TV_G_OUT TV_B_OUT TVOUT_FS Not used CVBS_OUT enable enable enable enable Not used ______________________________________________________________________________________ 31 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Table 11. Data Format for Read Mode REGISTER ADDRESS (hex) 0Eh BIT 7 Not used BIT 6 Power-on reset BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Not used ENC_Y_IN input video detection ENC_Y/ CVBS_IN input video detection VCR slow-switch input status VCR CVBS output load VCR CVBS input video detection TV slow switch input status TV CVBS output load TV CVBS input video detection 0Fh Not used Table 12. Register 00H: Audio Control DESCRIPTION TV Audio Mute 0 0 0 0 0 TV Volume Control 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 BIT 7 6 5 4 3 2 1 0 0 1 Off On (power-on default) 0dB gain (power-on default) -2dB gain -4dB gain -6dB gain -8dB gain -10dB gain COMMENTS ... TV Zero-Crossing Detector 0 1 Table 13. Register 01H: TV Audio DESCRIPTION BIT 7 6 5 4 3 2 1 0 Input Source for TV Audio 0 1 1 0 Input Source for VCR Audio 0 1 1 Interrupt Enable 0 1 0 1 0 1 0 0 1 0 1 VCR audio TV audio (MAX9671 only) Mute (power-on default) Encoder audio VCR audio TV audio (MAX9671 only) Mute (power-on default) Disabled (power-on default) Enabled COMMENTS Encoder audio ... 1 1 ... 1 1 ... 1 1 ... ... 1 1 0 1 ... ... -60dB gain -62dB gain Off On (power-on default) ... 32 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Table 14. Register 06H: TV Video Input Control DESCRIPTION BIT 7 6 5 4 3 2 0 0 0 Input Sources for TV Video 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 COMMENTS TV_Y/CVBS_OUT ENC_Y/CVBS_IN ENC_Y_IN VCR_Y/CVBS_IN TV_Y/CVBS_IN Not used Mute Mute Mute (power-on default) TV_G_OUT 0 Input Sources for TV_G_OUT and TV_B_OUT 0 1 1 0 1 0 1 ENC_G_IN VCR_G_IN Mute Mute (power-on default) Not used Mute Mute Mute (power-on default) TV_B_OUT ENC_B_IN VCR_B_IN Mute Mute (power-on default) TV_R/C_OUT ENC_R/C_IN ENC_C_IN VCR_R/C_IN Table 15. Register 07H: TV Video Output Control DESCRIPTION BIT 7 6 5 4 3 2 1 0 0 Set TV Slow Switching 1 1 0 Set TV Fast Switching 0 1 1 0 1 0 1 0 0 1 0 1 COMMENTS Low (< 2V) internal source Medium (4.5V to 7V); external SCART source with 16:9 aspect ratio High impedance (power-on default) High (> 9.5V); external SCART source with 4:3 aspect ratio GNDVID (power-on default) Not used Same level as VCRIN_FS VVID ______________________________________________________________________________________ 33 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Table 16. Register 08H: ENC and VCR Video Input/Output Control DESCRIPTION BIT 7 6 5 4 3 2 0 0 0 Input Sources for VCR Video 0 1 1 1 1 0 1 0 ENC R/C, G, and B inputs high-impedance bias (in HD application) 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 COMMENTS VCR_Y/CVBS_OUT ENC_Y/CVBS_IN ENC_Y_IN VCR_Y/CVBS_IN TV_Y/CVBS_IN Not used Mute Mute Mute (power-on default) VCR_R/C_OUT ENC_R/C_IN ENC_C_IN VCR_R/C_IN Mute Not used Mute Mute Mute (power-on default) ENC_R/C_IN Clamp/Bias DC restore clamp active at input (power-on default) Chrominance bias applied at input High-impedance bias off (power-on default) Biases the R/C, G, and B inputs to high impedance (overwrites the ENC_R/C_IN clamp and bias bit) DC restore clamp active at input (power-on default) Chrominance bias applied at input VCR_R/C_IN Clamp/Bias 0 1 34 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Table 17. Register 09H: VCR Video Output Control DESCRIPTION BIT 7 6 5 4 3 2 1 0 0 Set VCR Slow Switching 1 1 0 0 1 0 1 COMMENTS Low (< 2V) internal source Medium (4.5V to 7V); external SCART source with 16:9 aspect ratio High impedance (power-on default) High (> 9.5V); external SCART source with 4:3 aspect ratio Normal operation; pulldown on VCR_R/C_OUT is off (power-on default) Ground; pulldown on VCR_R/C_OUT is on; the output amplifier driving VCR_R/C_OUT is off 0 VCR_R/C_OUT Ground 1 Table 18. Register 0DH: Output Enable DESCRIPTION TVOUT_FS Enable TV_Y/CVBS_OUT Enable TV_B_OUT Enable TV_G_OUT Enable TV_R/C_OUT Enable VCR_R/C_OUT Enable VCR_Y/CVBS_OUT Enable 0 1 0 1 0 1 0 1 0 1 0 1 BIT 7 6 5 4 3 2 1 0 1 0 On Off (power-on default) On Off (power-on default) On Off (power-on default) On Off (power-on default) On Off (power-on default) On Off (power-on default) On COMMENTS Off (power-on default) ______________________________________________________________________________________ 35 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Table 19. Register 10H: Operating Modes DESCRIPTION BIT 7 0 6 0 5 4 3 2 1 0 Shutdown Standby mode (power-on default). Input video detection circuits are active. Audio circuitry is off unless video is detected. Once slow switch is detected, the signal paths between the VCR and TV SCART are connected. Full-power mode with input video detection and video-load detection active. Full-power mode without input video detection and video-load detection active. COMMENTS 0 1 Operating Mode 1 0 1 1 Table 20. Register 0EH: Status DESCRIPTION BIT 7 6 5 4 3 2 1 0 0 TV Slow-Switching Input Status 1 1 0 0 VCR Slow-Switching Input Status 1 1 0 Power-On Reset 1 VVID is high enough for digital logic to operate 0 1 0 1 0 0 1 0 1 COMMENTS 0 to 2V; internal source 4.5V to 7V; external source with 16:9 aspect ratio Not used 9.5V to 12.6V; external source with 4:3 aspect ratio 0 to 2V; internal source 4.5V to 7V; external source with 16:9 aspect ratio Not used 9.5V to 12.6V; external source with 4:3 aspect ratio VVID is too low for digital logic to operate 36 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Table 21. Register 0Fh: Video Activity Status DESCRIPTION TV CVBS Input Video Detection TV CVBS Output Load VCR CVBS Input Video Detection VCR CVBS Output Load ENC_Y/CVBS_IN Input Video Detection ENC_Y_IN Input Video Detection 0 1 0 1 0 1 0 1 0 1 BIT 7 6 5 4 3 2 1 0 0 1 COMMENTS No video detected. Video detected. No video detected. Video detected. No video detected. Video detected. No load connected. Load connected. No video detected. Video detected. No video detected. Video detected. ______________________________________________________________________________________ 37 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Typical Application Circuit 12V 0.1F 3.3V 0.1F 3.3V 0.1F V12 VVID VAUD TV_INL (MAX9671 ONLY) 7.68k +3.3 V STB CHIP TV_INR (MAX9671 ONLY) 2.55k 7.68k 2.55k MICROCONTROLLER SDA SCL INT DEV_ADDR TV_SS 75 TV_B_OUT VIDEO ENCODER TV_G_OUT ENC_Y/CVBS_IN 75 ENC_R/C_IN TVOUT_FS 75 ENC_G_IN 75 ENC_B_IN 75 ENC_Y_IN 75 ENC_C_IN 75 TV_Y/CVBS_OUT 0.1F TV_Y/CVBS_IN 75 75 75 TV_R/C_OUT 75 75 75 TV SCART TV_OUTL 75 TV_OUTR 75 MAX9670 MAX9671 GNDVID VCR_OUTR 75 7.68k VCR_INR 2.55k 1F STEREO AUDIO DACS VCR_OUTL 1F 6.65k ENC_INL VCR_INL 2.55k VCR_SS 1F 0.1F 6.65k ENC_INR VCR_B_IN 75 R1* VCR_G_IN 75 0.1F VCR_R/C_IN VCR_R/C_OUT 75 VCRIN_FS 75 0.1F 75 VCR SCART 75 7.68k 1F R1* *R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53k 1% DAC = PCM1742: R1 = 5.57k 1% VCR_Y/CVBS_OUT 0.1F C1P EP C1N CPVSS 1F 1F VCR_Y/CVBS_IN 75 75 38 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Pin Configurations VCR_R/C_IN VCR_R/C_IN TV_G_OUT TV_G_OUT TV_B_OUT TV_B_OUT VCR_G_IN ENC_G_IN VCR_B_IN VCR_G_IN ENC_G_IN ENC_B_IN VCR_B_IN ENC_B_IN VCRIN_FS GNDVID GNDVID TOP VIEW VVID VCRIN_FS MAX9670/MAX9671 TOP VIEW 33 32 31 30 29 28 27 26 25 24 ENC_C_IN 31 ENC_R/C_IN 32 TV_R/C_OUT 33 VCR_R/C_OUT 34 VCR _Y/CVBS_OUT 35 TV_Y/CVBS_OUT 36 VCR_Y/CVBS_IN 37 TV_Y/CVBS_IN 38 ENC_Y_IN 39 ENC_Y/CVBS_IN 40 1 SDA 2 SCL 3 DEV_ADDR 4 INT 5 VAUD 6 C1P 7 C1N 8 CPVSS 9 ENC_INL 10 ENC_INR *EP 20 TVOUT_FS 19 VCR_SS 18 V12 17 TV_SS 16 TV_OUTR ENC_C_IN ENC_R/C_IN TV_R/C_OUT VCR_R/C_OUT VCR_Y/CVBS_OUT TV _Y/CVBS_OUT VCR_Y/CVBS_IN TV_Y/CVBS_IN ENC_Y_IN ENC_Y/CVBS_IN N.C. 34 35 36 37 38 39 40 41 42 43 44 10 11 1 2 3 4 5 6 7 8 9 22 21 20 19 18 17 23 30 29 28 27 26 25 24 23 22 21 VVID N.C. TVOUT_FS VCR_SS V12 TV_SS TV_OUTR VCR_OUTR VCR_OUTL TV_OUTL VCR_INR VCR_INL TV_INR MAX9670 15 VCR_OUTR 14 VCR_OUTL 13 TV_OUTL 12 VCR_INR 11 VCR_INL MAX9671 16 15 14 *EP 13 12 VAUD CPVSS ENC_INL ENC_INR SDA SCL C1P C1N DEV_ADDR 40 TQFN *EP = EXPOSED PAD *EP = EXPOSED PAD 44 TQFN Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ TV_INL INT 39 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 40 TQFN 44 TQFN PACKAGE CODE T4066+3 T4477+2 DOCUMENT NO. 21-0141 21-0144 40 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Package Information (continued) For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. MAX9670/MAX9671 ______________________________________________________________________________________ 41 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Package Information (continued) For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 42 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Package Information (continued) For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. MAX9670/MAX9671 ______________________________________________________________________________________ 43 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Revision History REVISION NUMBER 0 1 REVISION DATE 7/09 3/10 Initial release Added Theta-A and Theta-C information in the Absolute Maximum Ratings section, adjusted Note references, updated power consumption Figures, and made various corrections DESCRIPTION PAGES CHANGED -- 1-8, 17, 20, 21, 22, 24-29, 33, 35, 36, 37 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 44 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. |
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